Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a semiconductor memory device and a semiconductor memory system including the semiconductor memory device.
A Double Data Rate 4 (DDR4) semiconductor memory device is configured to include a domain crossing margin (tDQSS) between a data strobe signal and a clock signal. Accordingly, the DDR4 semiconductor memory device may use a write leveling technology for calibrating a skew between the data strobe signal and the clock signal during a write operation.
A write leveling operation may be performed by entering a write leveling mode in response to a mode register set (MRS) and outputting a signal indicating the logic level state of a clock signal at a rising edge of a data strobe signal. More specifically, when a semiconductor memory device enters a write leveling mode, the semiconductor memory device compares the phase of an inputted data strobe signal with the phase of a clock signal and feeds the comparison result back to an external controller. Then, the external controller controls the phase of the data strobe signal based on the comparison result which is fed back from the semiconductor memory device.
The conventional write leveling operation has the following features. The semiconductor memory device compares the phase of the data strobe signal with the phase of a clock signal on a pad by pad basis. In other words, the phases of a pad-based data strobe signal and a pad-based clock signal are compared with each other. For this reason, the domain crossing margin (tDQSS) between the data strobe signal and the clock signal is secured only on the pad by pad basis. Therefore, the conventional write leveling operation may not reflect the actual write operation environment and may not stably secure the domain crossing margin (tDQSS) between the data strobe signal and the clock signal within a circuit where the write operation actually occurs. Here, securing the domain crossing margin (tDQSS) between a data strobe signal and a clock signal becomes more difficult in a high-frequency environment.
The conventional semiconductor memory device compares the phase of the data strobe signal with the phase of the clock signal at every toggling duration of the data strobe signal. More specifically, the conventional semiconductor memory device samples the phase state of the clock signal at every rising edge occurring in a toggling duration of the data strobe signal. However, if the phases are compared in the above-described method, time and current are consumed wastefully and the efficiency of the write leveling operation is decreased.